新思科技Synopsys ARC处理器研发实习生招聘芯片数字前端

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2025/5/8 14:32:10

SynopsysARC Processor R&D Intern Program

We are a teamworking on producing the highly optimized hardware IP for the ARC family ofconfigurable processors. We are looking for an engineer like you to be part ofthe team to work on our world-class micro-processors that allow our customersto develop highly optimized and sophisticated embedded designs. https://www.synopsys.com/designware-ip/processor-solutions.html

ASIC Digital R&DEngineer
Key responsibilities:
To develop and maintain our micro-processor hardware IP including specification, implementation,verification & FPGA validation
To optimize designs for performance, area and power
To develop new tests for hardware IP verification/validation and improvefunctional/code coverage by using state-of-the-art verification/validationmethodology
Interact with tools, modeling and simulation teams globally to deliver optimizedsolutions for our customers

Job Requirements:
Strong desire to work with embedded processors or processor-based systems
Knowledge of HDL design and ideally, RISC architectures, DSP, AI, multi-core, etc.
Understanding of design/verification languages such as, SystemVerilog, Verilog
Knowledge of tools such as, RTL Simulators, e.g. VCS
Familiar with FPGA design flow and tools (Synplify, Vivado, Quartus), includingconstraint setup, synthesis, P&R and timing closure
Scripting/programming skill in assembler, C, Tcl, Perl/Csh desired
Good analysis and problem-solving skills
Excellent written and verbal skills including: Written and spoken English, Detailedstatus reporting; Ability to present results to the program management teams


新思科技Synopsys ARC处理器研发实习生-芯片&FPGA&数字前端
实习期：3~12个月及以上
对于有在企业完成毕业论文需求的长期实习生，可指定企业导师并全程跟踪指导毕业论文，包括选题，开题，技术探讨等
实习地点：武汉东湖高新技术开发区-新思科技武汉全球研发中心
简历发送至 snps_arcc@synopsys.com



超一流的工作氛围和办公环境：
聚焦行业热点前沿技术，全球化协同开发，与欧美资深团队零距离交流；
办公室采用全自动升降式办公桌，休息室、健身房、瑜伽房、 淋浴间 一应俱全；
每周五下午集体运动（羽毛球、篮球、瑜伽等），双周茶话会，月度生日会、团建旅游等；